1. Field of the Invention
The present invention pertains to metal-oxide-semiconductor field effect (MOS) devices and methods for manufacturing MOS devices and integrated circuits including them. In preferred embodiments, the invention pertains to methods for manufacturing p-channel MOS devices (PMOS devices) to reduce or eliminate the dependence of their drain breakdown voltage on stress factors (e.g., temperature stress and/or voltage stress).
2. Description of the Related Art
The expression “MOS device” is used herein as a synonym for an MOS transistor.
Commonly, power management circuits (e.g., DC-DC converters and other circuits for smart power management applications) are required to operate at high voltages (e.g., in the 50V to 100V range). Some such circuits are manufactured in accordance with a BiCMOS process and include bipolar, PMOS, NMOS, and power DMOS (double diffused metal oxide semiconductor) devices on a single chip, including low to medium voltage (5V-15V) as well as high voltage devices. In such circuits the high voltage PMOS (“HV-PMOS”) transistors must be able to operate at high currents, high voltages (e.g. 80V) and high temperatures (150° C.) while sustaining a drain breakdown voltage well in excess of the device operating voltage. In a typical high power application the HV-PMOS devices are expected to operate at a gate voltage of 14V, a drain voltage of 80V and a temperature of 150° C. while having a drain breakdown voltage (Bvdss) well above 80V. Because of the high voltages, currents and temperatures seen by these devices the long-term reliability is a key concern.
FIG. 1 is a cross-sectional view of a conventional HV-PMOS device manufactured in accordance with a BiCMOS process, including gate 1, source 2, drain 3, N-type epitaxial layer 4, gate oxide 5 under gate 1, and N-type substrate 8. Gate oxide 5 consists of silicon dioxide having a thickness of 38 nm. The FIG. 1 device differs from a traditional MOS device in that it has an asymmetric device architecture that includes an extended drain region consisting of a P-type lightly doped drain (P-LDD) implant 6 and a P-type deep drain (P-Body) implant 7 in layer 4. P-LDD implant 6 and P-Body implant 7 increase the device's drain breakdown voltage and thus increase its maximum operational voltage. Critical device parameters include the length of gate 1, and the doping concentration and length of P-LDD implant region 6 since these must sustain the high voltages (e.g., 100 V) to be applied to the device.
The expression “hot carrier ionization” (in an MOS device) is used herein to denote the phenomenon that energetic (“hot”) carriers in the drain or extended drain region or body of the device (e.g., in a well/drain depletion region) ionize atoms (usually silicon atoms) in the drain or extended drain region or body, thereby creating electron-hole pairs. The carriers can be electrons or holes.
The expression “maximum impact ionization point” is used herein to denote the region in an MOS device in which the probability of hot carrier ionization exceeds an appropriately defined threshold.
The expression “drain breakdown” (of an MOS device) is used herein to denote the avalanche breakdown of a p-n junction at the drain (or extended drain region) of the device. If the device has an extended drain region including a drain, a lightly doped drain (P-LDD) implant, and a P-type deep drain (P-Body) implant, the p-n junction at which breakdown occurs can be at the P-LDD implant or the P-Body implant. In cases when drain breakdown has occurred, increased current flows to or from the drain when the device's gate, source, and substrate are grounded.
The expression drain junction “breakdown point” (or drain junction “breakdown location”) is used herein to denote the region in an MOS device in which drain breakdown occurs. The “maximum impact ionization point” of a device can but need not coincide with the device's drain junction “breakdown point.”
Throughout this disclosure, the expression “drain breakdown voltage” (or “Bvdss”) of an MOS device denotes the minimum absolute value of the drain voltage (VDS) with the gate, source and substrate grounded that causes the device to exhibit drain breakdown, where VDS is the potential applied to the device's drain relative to the source.
The expressions Bvdss “walk-in” and Bvdss “walk-out” are used herein as follows with reference to an MOS device that has undergone stress: Bvdss “walk-in” denotes the phenomenon that the magnitude of the device's post-stress drain breakdown voltage is less than its pre-stress drain breakdown voltage; and Bvdss “walk-out” denotes the phenomenon that the magnitude of the device's post-stress drain breakdown voltage is greater than its pre-stress drain breakdown voltage.
Drain breakdown voltage walk-in (Bvdss walk-in) can cause functional PMOS device failure, such as during high temperature (e.g., 150° C.) operation as may occur in operational lifetime testing.
It has been known that application of stress to a PMOS device can cause Bvdss walk-in. However, it had not been known until the present invention what parameters of the design (or method of fabricating) a PMOS device are critical to reducing or eliminating its susceptibility to Bvdss walk-in. Nor had it been known until the present invention how to perform modification to the design of a PMOS device (or modification to its fabrication method) to reduce or eliminate the device's susceptibility to Bvdss walk-in. For example, it had not been known until the present invention how to modify a parameter of an ion implantation process employed to fabricate an extended drain region of a PMOS device to reduce (or eliminate) the device's susceptibility to Bvdss walk-in.